1. Field of the Invention
This invention relates to a dual-injection locked frequency dividing circuit which is designed for use with a gigahertz signal processing system, particularly of the type that operates in the frequency range from 35.7 GHz to 54.9 GHz (gigahertz), for providing a frequency dividing function to gigahertz signals.
2. Description of Related Art
With the advent of wireless digital communication technologies, such as wireless networking, mobile phones, GPS (Global Positioning System), and digital TV, the design and manufacture of high-speed digital circuit boards that operate with signals within the gigahertz range is in high demand in the electronics industry. Nowadays, the operating frequency of high-speed digital circuitry has advanced to the ranges of RF (radio frequency), microwave, and millimeter waves.
In the design of high-speed digital circuitry, frequency dividers are an important component that can convert a fixed signal frequency to a lower frequency. For high performance application purposes, the design of frequency divider circuitry typically requires a broader frequency locking range. Beside, in mobile applications, since mobile devices are battery-powered, the design of frequency divider circuitry for use in mobile devices further requires low power consumption.
Presently, in RF applications, the ILFD (injection-locked frequency divider) circuit architecture is a widely used technology. However, in practice, one drawback to the ILFD circuit architecture is that it can only offer a narrow frequency locking range which would be unsatisfactory and inadequate for use in broadband applications.
In view of the above-mentioned drawbacks of the prior art, it is an research effort in academic research institutes and electronics industry for a new and improved frequency divider circuit architecture which can operate with broad frequency locking range and low power consumption. Some research results have been disclosed in the following technical papers: (1) “Superhamonic Injection-Locked Frequency Dividers”, authored by H. R. Rategh et al and published on IEEE Journal of Solid-State Circuits, Vol. 34, pp. 813-821, June 1999); (2) “A 19 GHz 0.5 mW 0.35 μm CMOS Frequency Divider with Shunt-Peaking Enhancement”, authored by Hui Wu et al and published on IEEE International Solid-State Circuits Conference, pp. 412-413, 417, February 2001); and (3) “55 GHz CMOS Frequency Divider with 3.2 GHz Locking Range”, authored by K Yamamoto et al and published on Proc. 30th European Solid-State Circuits Conference, ESSCIRC 2004, pp. 135-138, September 2004).
Among the above-listed papers, H. R. Rategh et al teaches a frequency divider circuit architecture that operates at 3 GHz with a frequency locking range of 370 MHz; Hui Wu et al teaches a circuit architecture that operates at 19 GHz with a frequency locking range of 1.35 MHz; and K Yamamoto et al teaches still another circuit architecture that operates at 55 GHz with a frequency locking range of 3.2 GHz.
For broadband applications within the range from 35.7 GHz to 54.9 GHz, the frequency divider circuit architecture disclosed by K Yamamoto et al is a suitable technology. However, still one drawback of this technology is that its frequency locking range is only 3.2 GHz, which is still unsatisfactory and inadequate for use in such broadband applications.